IEEE 1149.1-2013 PDF
This standard defines test logic that can be included in an integrated circuit to provide standardized approaches to: Testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate – Testing the integrated circuit itself – Observing or modifying circuit activity during the component’s normal operation The test logic consists of a boundary-scan register and other building blocks and is accessed through a test access port (TAP).
This subclause provides a general overview of the operation of a component compatible with this standard and provides a background to the detailed discussion in later clauses. The circuitry defined by this standard allows test instructions (which take control of the component outputs and observe the component inputs) and associated test data to be fed into a component and, subsequently, allows the results of execution of such instructions to be read out. All information (instructions, test data, and test results) is communicated in a serial format
Revision Standard – Inactive-Reserved. Circuitry that may be built into an integrated circuit to assist in the test, maintenance and support of assembled printed circuit boards and the test of internal circuits is defined. The circuitry includes a standard interface through which instructions and test data are communicated. A set of test features is defined, including a boundary-scan register, such that the component is able to respond to a minimum set of instructions designed to assist with testing of assembled printed circuit boards. Also, a language is defined that allows rigorous structural description of the component-specific aspects of such testability features, and a second language is defined that allows rigorous procedural description of how the testability features may be used.
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